![]() If(ld) st_nxt = 13'd0 //the circuit is designedĮlse if(en) st_nxt = st + 1 //to load only 0 `timescale 1ns/1nsĬounter cut(.clk(clk).rst(rst).en(en).out(out)) ![]() I posted the Verilog source code and the diagram ( diagram ). My question is why the output of the circuit is incremented twice after each millisecond elapsed(and not only once, as expected). Besides, the second circuit receives a load signal(when active, the load produces a low-logic). The circuit(module numarator) consists of two blocks: a circuit which receives a 5MHz frequency clock signal(module counter), and is supposed to produce a high-logic every 5000cct passed(the equivalent of 1ms, thus producing output high after every millisecond), and another circuit which receives the same clock signal and counts the number of elapsed milliseconds(module preset). ![]() I have built a circuit that is supposed to count the milliseconds. I have a problem when running this piece of Verilog code in ModelSim.
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